G.M.R.T. CLOCK CIRCUIT

1.DDS :
We used AD9851 direct digital synthesiser ( DDS ) for buildind the clock / synchronisation signal generation circuit. The frequency resolution of the device is f_clk / 2³² and the phase resolution is 360° / 2⁵ = 11°25'. Here f_clk is the clock frequency of the DDS. We have chosen f_clk as 105MHz, which will be taken from the local oscillator system of the GMRT. Since the phase of the clock be controlled in the DDS it is ideal for our application.
2.Block Diagram :
The block diagram of the circuit is given below. DDS1 and DDS2 ae used to generate te two clocks f₁ and f₂. An EPLD ( EPM7064 ) base circuit is used to preset the clocks to 32 and 32.25MHz when powered on. It is also used to interface a computer to the DDS.
The outputs of the DDSs are passed through a 40MHz low pass filter. The filtered outputs are converted to compatible square waves using the internal comparators in the DDSs. A modulo 128 and a modulo 129 counters, which are implemented in the PAL 22V10 devices, are clocked bu the 32 and 32.25MHz outputs respectively. A circuit PAL16V8 enables these two counters twenty three f_clk cycles after the DDSs are programmed ( i.e. after the signal FQ_UD is activated ). To check the frequencies f₁ and f₂ are in the ratio 128 / 129, a feed back circuit is implemented using an XOR logic. On the generation of the feed back signal the frequency words which are present in the nternal registers of the DDSs are reloaded. This feed back circuit also generates an interrupt to the PC and a signal which can be read by the PC through the parallel port. The interrupt signal is several msec wide. The signal which is sent to PC through the parallel port stays active till the computer sends an acknowledgment.
3.Circuit Diagram :
The Circuit Diagram for the DDS based clock / synchronisation signal generator is shown below. The schematic of the circuit implemented in the EPLD EPM7064. It has two functions.
   a.To preset the DDSs to frequencies 32 and 32.25MHz when powered on or reset from computer. The signal timings and the frequency words loaded to the DDSs at this stage are given in "frequency words".
   b.After presetting the DDSs the EPLD gives the control ( control signal enable ) to the computer and provides the necessary interfacing circuits. The simulation results of the EPLD circuit is given in "simulation results".
   c.The modulo 128 and 129 counters and the feed back circuit ( carry_check ) are implemented in PAL22V10s and PAL16V8s are also attached.

Block Diagram	Circuit Diagram	Schematic	Simulation Results

GOBACK TO CLOCK SUBSYSTEM
GOTO DIGITAL BACKEND